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DMA controller (DMA)
RM0008
If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as
soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx register.
The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory
mode may not be used at the same time as Circular mode.
10.3.4
Table 55.
Programmable data width, data alignment and endians
When PSIZE and MSIZE are not equal, the DMA performs some data alignments as
described in Table 55: Programmable data width & endian behavior (when bits PINC =
MINC = 1) .
Programmable data width & endian behavior (when bits PINC = MINC = 1)
Number
Source
port
width
Destination
port width
of data
items to
transfer
Source content:
address / data
Transfer operations
Destination
content:
address / data
(NDT)
@0x0 / B0
1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0
@0x0 / B0
8
8
4
@0x1 / B1
@0x2 / B2
2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1
3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2
@0x1 / B1
@0x2 / B2
@0x3 / B3
@0x0 / B0
4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3
1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0
@0x3 / B3
@0x0 / 00B0
8
16
4
@0x1 / B1
@0x2 / B2
2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2
3: READ B3[7:0] @0x2 then WRITE 00B2[15:0] @0x4
@0x2 / 00B1
@0x4 / 00B2
@0x3 / B3
@0x0 / B0
4: READ B4[7:0] @0x3 then WRITE 00B3[15:0] @0x6
1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0
@0x6 / 00B3
@0x0 / 000000B0
8
32
4
@0x1 / B1
@0x2 / B2
2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4
3: READ B3[7:0] @0x2 then WRITE 000000B2[31:0] @0x8
@0x4 / 000000B1
@0x8 / 000000B2
@0x3 / B3
@0x0 / B1B0
4: READ B4[7:0] @0x3 then WRITE 000000B3[31:0] @0xC
1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0
@0xC / 000000B3
@0x0 / B0
16
8
4
@0x2 / B3B2
@0x4 / B5B4
2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1
3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2
@0x1 / B2
@0x2 / B4
@0x6 / B7B6
@0x0 / B1B0
4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3
1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0
@0x3 / B6
@0x0 / B1B0
16
16
4
@0x2 / B3B2
@0x4 / B5B4
2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2
3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
@0x0 / B1B0
4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6
1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0
@0x6 / B7B6
@0x0 / 0000B1B0
16
32
4
@0x2 / B3B2
@0x4 / B5B4
2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4
3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8
@0x4 / 0000B3B2
@0x8 / 0000B5B4
@0x6 / B7B6
@0x0 / B3B2B1B0
4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC
1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0
@0xC / 0000B7B6
@0x0 / B0
32
8
4
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1
3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2
@0x1 / B4
@0x2 / B8
@0xC / BFBEBDBC
@0x0 / B3B2B1B0
4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3
1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[7:0] @0x0
@0x3 / BC
@0x0 / B1B0
32
16
4
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[7:0] @0x1
3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[7:0] @0x2
@0x2 / B5B4
@0x4 / B9B8
@0xC / BFBEBDBC
@0x0 / B3B2B1B0
4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[7:0] @0x3
1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0
@0x6 / BDBC
@0x0 / B3B2B1B0
32
32
4
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4
3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC
@0xC / BFBEBDBC
Addressing an AHB peripheral that does not support byte or halfword write
operations
When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on
the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does
186/995
Doc ID 13902 Rev 9
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